Continuing scaling of the CMOS fabrication process to allow increasing number of devices on a VLSI chip has caused ‘within-die’ variations to become a significant problem. These within-die variations result from manufacturing process variations such as Le (the effective channel length) and Vt (threshold voltage) as well as supply voltage and temperature variations. Within-die variations cause an undesirable uncertainty with respect to on-chip signal timing. Conventional timing analysis for VLSI chips uses different values for process, voltage, and temperature corners (maximum allowable combinations of these values) for maximum and minimum signal delay analysis. Such an approach often leads to ‘overdesigning’, which may cause unnecessarily high power requirements and reliability problems.
Previously existing methods for interconnect coupling analysis have typically used Monte Carlo simulation statistical analysis techniques. However, Monte Carlo simulation takes an extremely long time and does not provide a realistic solution for analyzing complex VLSI circuits. Nearly all existing analytical methods deal exclusively with variations in active devices such as transistors and logic gates. With the increasing aspect ration of device interconnects, coupling between the interconnects and its impact on signal transmission have played an increasing role in VLSI circuit analysis. A signal path from a point on a chip to another point on the chip consists not only of logic gates and other devices, but also includes the interconnects between the devices. As CMOS technology continues to scale, the proportion of the total signal delay time attributable to interconnect delay increases. Therefore, the importance of accuracy of modeling interconnect delay becomes increasingly important. In addition to accuracy limitations, existing simulation methods incorporating linear Taylor expansion cannot be directly applied to multi-aggressor, partial coupling cases, which are common in real applications.